*) Design planning
*) Design specification, implementation, and verification
*) Software testing and documentation
*) proof of concept on an existing design
*) Excellent scripting skills in Perl
*) Continuous Integration and Jenkins
*) Experience in ASIC design using VHDL and System Verilog and RTL integration
*) Experiences in software testing
*) Master of Science or similar
*) Knowledge about compiler development is a plus
*) Knowledge about Agile (Scrum) ways of working
*) Knowledge about Formal verification is a plus
*) Knowledge of ASIC/FPGA verification methodology in general
Please apply by sending your CV to [email protected]. Remember to address all of the required competence areas in your CV.
We are looking forward to your application and to meet you in Lund.